1. Field of the Invention
The present invention relates to a semiconductor device in which the backside surface (or lower surface) edges are chamfered to increase the deflective strength of a semiconductor chip and a method of manufacturing the same.
2. Description of the Related Art
As shown in FIG. 1, the edges between side surfaces 11-1 to 11-4 and a backside surface 11A of a semiconductor chip 11 generally have a number of three-dimensional patterns of chippings 12 formed at the time of dicing. FIGS. 2A, 2B, and 2C are SEM (Scanning Electron Microscope) photographs of the semiconductor chip 11. FIGS. 2A and 2B are SEM photographs of one corner portion of the semiconductor chip 11 viewed from the side of the backside surface 11A. FIG. 2C is an SEM photograph of the semiconductor chip 11 viewed from a side surface.
As described above, the edges of the conventional semiconductor chip 11 have a number of defects due to chippings in the dicing process or the like.
For this reason, when a pressure F is applied to the side of an element formation surface 11B, as shown in FIG. 3A, the semiconductor chip 11 readily breaks from the chipping 12, as shown in FIG. 3B. The pressure F is generated when the semiconductor chip is picked up and mounted on, e.g., a lead frame or TAB tape in a mount process, or due to the difference in thermal expansion properties between the package material and the semiconductor chip 11. When the pressure F is applied to the side of the element formation surface 11B, stress concentration on the chipping 12 occurs. Hence, the semiconductor chip 11 breaks from the chipping 12.
To decrease the number of chippings at the edges of the backside surface 11A of the semiconductor chip 11, a technique called a DBG (Dicing Before Grinding) method has been proposed (e.g., Jpn. Pat. Appln. KOKAI Publication No. 61-112345). When this technique is used, the chippings 12 generated at the edges between the backside surface 11A and the side surfaces 11-1 to 11-4 of the semiconductor chip 11 can greatly be suppressed, as shown in FIG. 4. FIGS. 5A, 5B, and 5C are SEM photographs of the semiconductor chip 11 formed using the DBG method. FIGS. 5A and 5B are SEM photographs of one corner portion of the semiconductor chip 11 viewed from the side of the backside surface 11A. FIG. 5C is an SEM photograph of the semiconductor chip 11 viewed from a side surface.
However, when the semiconductor chip 11 is thin (e.g., 100 μm or less) or long, stress concentrates at the edges of the backside surface 11A of the semiconductor chip 11 even when no chippings 12 are present. Hence, the strength of the semiconductor chip 11 considerably decreases.
Hence, the semiconductor chip 11 breaks during the assembly process up to when the semiconductor chip 11 is packaged or at the time of reliability test, resulting in a defective chip.